1. Field of the Invention
Embodiments of the present invention relate to data throughput regarding a storage device and a processor device. More specifically, embodiments of the present invention relate to increasing data throughput between a microprocessor and a data storage device having sequential data access.
2. Related Art
Flash memory devices have become widely used as storage devices for many electronic systems, including consumer electronic devices. These non-volatile memory devices can store relatively large amounts of data while being relatively small in size. Flash memory device manufacturers have provided a variety of communication interface protocols for their devices to allow efficient signaling. However, some flash memory communication interfaces do not allow optimum data throughput between the memory device and a processor accessing data therefrom. More specifically, some flash memory devices are sequentially accessed devices, also known as serial block devices. These devices do not have a separate address bus. Instead, the desired address is loaded into the data bus and special commands indicate to the memory device that an address is present on the data bus. In read mode (also entered by a special command), this causes the flash memory to supply data onto the data bus starting at the loaded addresses and then incrementing through sequential addresses. The data is supplied at a strobe rate defined by various other timing signals, e.g., data output enable, etc., which may originate from the processor.
For instance, processors having a data cache typically increase data access performance by caching recently received data and then subsequently providing that data directly from the data cache when the processor requests it again, thereby avoiding delays associated with bus access requests and external device delays. However, when a processor enables its data cache for use in conjunction with the flash memory device described above, data coherency problems arise. In this configuration, when the processor begins to receive sequential data from the flash memory, its read pointer remains fixed to the start address that was loaded into the flash memory. This is the case because the flash memory has no address bus and may be “addressed” by the processor using a single address value. If the data cache is enabled, each subsequent read request, after the first one, would therefore involve a data cache hit because the same address is involved for each read. As a result, the data cache, and not the flash memory, would then keep supplying the first received data for each subsequent read cycle. In other words, after the first data was received from the flash memory, all other data would be ignored by the processor during the read transaction.
One solution to this problem is to disable the data cache during read operations from the flash memory. This solution is not desired because it introduces unwanted data latency. If the data cache is disabled, then the processor typically issues a bus access request in between receiving each byte of data from the flash memory. The instructions for reading the flash memory contents, in this case, are issued sequentially without pipelining and without data prefetch efficiencies. In short, this solution while eliminating the data coherency problems described above does not provide adequate data throughput for many applications and data block sizes.
Lastly, another solution to the above data coherency problem is to flush the data cache after each data is received from the flash memory. However, this solution is not desired because it eliminates the efficiencies provided by the data cache regarding other processor functions, e.g., with respect to other devices not involving the flash memory. Also, cache flushing adds more data latency because the processor consumes cycles to perform the flush and this flush must be performed after each data is received.